# Enable internal termination resistor on LVDS 125MHz ref_clk
set_property DIFF_TERM TRUE [get_ports ref_clk_clk_p]
set_property DIFF_TERM TRUE [get_ports ref_clk_clk_n]

# Define I/O standards
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_0_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ref_clk_fsel[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_1_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_0_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports reset_port_0]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ref_clk_oe[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_1_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_2_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[3]}]
set_property IOSTANDARD LVDS [get_ports ref_clk_clk_p]
set_property IOSTANDARD LVDS [get_ports ref_clk_clk_n]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_txc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_txc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports reset_port_1]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_txc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_2_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports reset_port_2]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_txc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_3_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_3_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports reset_port_3]

set_property PACKAGE_PIN H1 [get_ports {rgmii_port_1_rd[0]}]
set_property PACKAGE_PIN G1 [get_ports mdio_io_port_0_mdio_io]
set_property PACKAGE_PIN D2 [get_ports {rgmii_port_1_rd[2]}]
set_property PACKAGE_PIN G8 [get_ports {ref_clk_fsel[0]}]
set_property PACKAGE_PIN G7 [get_ports mdio_io_port_1_mdio_io]
set_property PACKAGE_PIN U2 [get_ports rgmii_port_3_rxc]
set_property PACKAGE_PIN U1 [get_ports rgmii_port_3_rx_ctl]
set_property PACKAGE_PIN R3 [get_ports {rgmii_port_3_rd[1]}]
set_property PACKAGE_PIN R2 [get_ports {rgmii_port_3_rd[3]}]
set_property PACKAGE_PIN D3 [get_ports rgmii_port_1_rxc]
set_property PACKAGE_PIN C3 [get_ports rgmii_port_1_rx_ctl]
set_property PACKAGE_PIN E8 [get_ports mdio_io_port_0_mdc]
set_property PACKAGE_PIN D8 [get_ports reset_port_0]
set_property PACKAGE_PIN A2 [get_ports {rgmii_port_1_rd[1]}]
set_property PACKAGE_PIN A1 [get_ports {rgmii_port_1_rd[3]}]
set_property PACKAGE_PIN A5 [get_ports {ref_clk_oe[0]}]
set_property PACKAGE_PIN A4 [get_ports mdio_io_port_1_mdc]
set_property PACKAGE_PIN T2 [get_ports rgmii_port_2_rxc]
set_property PACKAGE_PIN N4 [get_ports {rgmii_port_2_rd[2]}]
set_property PACKAGE_PIN N3 [get_ports {rgmii_port_2_rd[3]}]
set_property PACKAGE_PIN N1 [get_ports {rgmii_port_3_rd[0]}]
set_property PACKAGE_PIN P1 [get_ports {rgmii_port_3_rd[2]}]
set_property PACKAGE_PIN B4 [get_ports rgmii_port_0_rxc]
set_property PACKAGE_PIN B3 [get_ports rgmii_port_0_rx_ctl]
set_property PACKAGE_PIN G6 [get_ports {rgmii_port_0_rd[2]}]
set_property PACKAGE_PIN F6 [get_ports {rgmii_port_0_rd[3]}]
set_property PACKAGE_PIN D1 [get_ports {rgmii_port_0_td[1]}]
set_property PACKAGE_PIN C1 [get_ports {rgmii_port_0_td[2]}]
set_property PACKAGE_PIN E7 [get_ports {rgmii_port_1_td[0]}]
set_property PACKAGE_PIN B7 [get_ports {rgmii_port_1_td[2]}]
set_property PACKAGE_PIN B6 [get_ports {rgmii_port_1_td[3]}]
set_property PACKAGE_PIN J3 [get_ports rgmii_port_2_rx_ctl]
set_property PACKAGE_PIN K2 [get_ports {rgmii_port_2_rd[0]}]
set_property PACKAGE_PIN L2 [get_ports {rgmii_port_2_td[1]}]
set_property PACKAGE_PIN L1 [get_ports {rgmii_port_2_td[2]}]
set_property PACKAGE_PIN M2 [get_ports rgmii_port_2_tx_ctl]
set_property PACKAGE_PIN M1 [get_ports mdio_io_port_2_mdio_io]
set_property PACKAGE_PIN R4 [get_ports {rgmii_port_3_td[0]}]
set_property PACKAGE_PIN P6 [get_ports {rgmii_port_3_td[2]}]
set_property PACKAGE_PIN P5 [get_ports {rgmii_port_3_td[3]}]
set_property PACKAGE_PIN D5 [get_ports ref_clk_clk_p]
set_property PACKAGE_PIN C4 [get_ports ref_clk_clk_n]
set_property PACKAGE_PIN E4 [get_ports {rgmii_port_0_rd[0]}]
set_property PACKAGE_PIN E3 [get_ports {rgmii_port_0_rd[1]}]
set_property PACKAGE_PIN B2 [get_ports {rgmii_port_0_td[0]}]
set_property PACKAGE_PIN B1 [get_ports rgmii_port_0_txc]
set_property PACKAGE_PIN C6 [get_ports {rgmii_port_0_td[3]}]
set_property PACKAGE_PIN C5 [get_ports rgmii_port_0_tx_ctl]
set_property PACKAGE_PIN D7 [get_ports {rgmii_port_1_td[1]}]
set_property PACKAGE_PIN D6 [get_ports rgmii_port_1_txc]
set_property PACKAGE_PIN A7 [get_ports rgmii_port_1_tx_ctl]
set_property PACKAGE_PIN A6 [get_ports reset_port_1]
set_property PACKAGE_PIN J2 [get_ports {rgmii_port_2_rd[1]}]
set_property PACKAGE_PIN J1 [get_ports {rgmii_port_2_td[0]}]
set_property PACKAGE_PIN P7 [get_ports rgmii_port_2_txc]
set_property PACKAGE_PIN R7 [get_ports {rgmii_port_2_td[3]}]
set_property PACKAGE_PIN P3 [get_ports mdio_io_port_2_mdc]
set_property PACKAGE_PIN P2 [get_ports reset_port_2]
set_property PACKAGE_PIN L6 [get_ports {rgmii_port_3_td[1]}]
set_property PACKAGE_PIN M6 [get_ports rgmii_port_3_txc]
set_property PACKAGE_PIN J7 [get_ports rgmii_port_3_tx_ctl]
set_property PACKAGE_PIN J6 [get_ports mdio_io_port_3_mdc]
set_property PACKAGE_PIN J8 [get_ports mdio_io_port_3_mdio_io]
set_property PACKAGE_PIN K8 [get_ports reset_port_3]

create_clock -period 8.000 -name rgmii_port_3_rx_clk -waveform {0.000 4.000} [get_ports rgmii_port_3_rxc]

create_clock -period 8.000 -name ref_clk_clk_p -waveform {0.000 4.000} [get_ports ref_clk_clk_p]

# IODELAY group for GMII-to-RGMII block
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells *_i/gmii_to_rgmii_0/U0/i_*_gmii_to_rgmii_0_0_idelayctrl]
set gmii_to_rgmii_0_iodelay [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.IODELAY.IDELAYE2 && NAME =~  "*/gmii_to_rgmii_0/*delay_rgmii_rx*" } ] 
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 $gmii_to_rgmii_0_iodelay
set_property IDELAY_VALUE 13 $gmii_to_rgmii_0_iodelay

# IODELAY groups for AXI Ethernet ports
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells *_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells {*_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx* {*_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}}]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells {*_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/delay_rgmii_rx* {*_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}}]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells {*_i/axi_ethernet_2/inst/mac/inst/rgmii_interface/delay_rgmii_rx* {*_i/axi_ethernet_2/inst/mac/inst/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}}]

#False path constraints to async inputs coming directly to synchronizer
set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_reset_gen/*reset_sync*/PRE }]
set_false_path -to [get_pins -of [get_cells -hier -filter { name =~ *i_MANAGEMENT/SYNC_*/data_sync* }] -filter { name =~ *D }]
set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
#False path constraints from Control Register outputs
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/DUPLEX_MODE_REG*/C }]
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/SPEED_SELECTION_REG*/C }]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/CE0}]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/S0}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/CE1}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/S1}]

# IDELAY values for port 1
set_property IDELAY_VALUE 13 [get_cells {*/axi_ethernet_1/inst/mac/inst/rgmii_interface/rxdata_bus[0].delay_rgmii_rxd}]
set_property IDELAY_VALUE 13 [get_cells {*/axi_ethernet_1/inst/mac/inst/rgmii_interface/rxdata_bus[1].delay_rgmii_rxd}]
set_property IDELAY_VALUE 13 [get_cells {*/axi_ethernet_1/inst/mac/inst/rgmii_interface/rxdata_bus[2].delay_rgmii_rxd}]
set_property IDELAY_VALUE 13 [get_cells {*/axi_ethernet_1/inst/mac/inst/rgmii_interface/rxdata_bus[3].delay_rgmii_rxd}]
set_property IDELAY_VALUE 13 [get_cells {*/axi_ethernet_1/inst/mac/inst/rgmii_interface/delay_rgmii_rx_ctl}]

